application note mk5025 transparent mode introduction the sgs-thomson x.25 link level controller (mk5025) is a vlsi device which provides a com- plete link level data communication control con- forming to the 1984 ccitt version of x.25. the mk5025 also supports x.32 (xid) and x.75 as well as single channel lapd for isdn with its ui frames and extended addressing capabilities. one of the outstanding features of the mk5025 is its buffer managment which includes on-chip dma. this feature allows users to handle multi- ple frames of receive and transmit data at a time. in order to utilize these buffer managment and dma features with protocols not directly sup- ported by the mk5025, a transparent mode is available for customized protocols using hdlc framing. this transparent mode provides an hdlc transport mechanism without link layer support. extended addressing and control are optionally supported within transparent mode. address filtering is also optional in this mode. purpose the purpose of this application brief is to provide a detailed description of the mk5025 transparent mode and its options. please refer to the mk5025 technical manual for more detailed in- formation concerning the overall operation of the mk5025. transparent mode entry and exit to enter the transparent mode of operation, a user primitive trans (uprim 3) is written to con- trol status register 1 (csr1) af ter the completion of the first 4 steps of the initialization procedure described in page 4-24 of the mk5025 technical manual. (the trans primitive is substituted for the start primitive.) the transmitter then begins to output flags, and data frames are transmitted and received via the descriptor rings, but no protocol processing is done. address and control fields are not prepended to the frames, and fcs (frame check sequence) processing may be en- abled or disabled by the drfcs and dtfcs bits in the mode register, as described on page 4-12 of the technical manual. transparent mode may be exited only with a stop primitive (uprim 0) or by bus reset. control and status register operation in transparent mode all the control and status reg- ister mechanisms are still functional, but there are several bits that pertain only to the protocols di- rectly supported by the mk5025 and are not valid in transparent mode. the following is a list of the validity of the bits in each csr and the mode reg- ister when in transparent mode. csr0 - all bits in this register are valid in trans- parent mode. it should be noted that interrupts can only be set (by setting bit 09, inea = 1) once the device is in start or transparent mode. csr1 - all bits except pparm are valid, although only for a few non-protocol related conditions. since in transparent mode only a stop user primitive would have been valid, user primitives 8 and 9 have been redefined. when in transparent mode, issuing user primitive 8 (uprim 8) will start t1 timer and user primitive 9 (uprim 9) will stop it. in this case provider primitive 8 (pprim 8) has been redefined to indicate expiry of t1 timer. csr2 - aside from the iadr bits, only the prom and xide bits have valid meaning in transparent mode. the xide bit can be set to 1 to enable global address recognition, and the prom bit is used to disable address filtering in transparent mode. csr3 - as in csr2, the iadr bits contain the ad- dress of the first word in the initialization block. bits 00 - 07 in csr2 contain the high order 8 bits, and bits 00 - 15 of csr3 contain the low order 16 bits of the address of the first word of the initiali- zation block. csr4 - all bits in this register are valid in trans- parent mode, including the fifo watermarks and bursting operations. csr5 - all bits are valid in transparent mode. mode register operation all bits in the mode register are valid including mfs (minimum frame spacing) and lback (loopback). however, bits 09 (extaf) and 10 (extcf) are useful mainly in transparent mode, for forcing extended address and control f ield fil- tering. the dace bit also offers further flexibility in transparent mode by allowing address and con- AN493/0592 1/4
trol fields to be treated as normal data when dace = 1, as shown in table 2. it should be noted that although dtfcs and drfcs (bits 04 & 05) may be used to disable fcs generation and checking, the value in the fcs field of the received frame will not be stored in memory, even in transparent mode. descriptor ring operation the buffer management and descriptor ring op- eration is the same in transparent as non-trans- parent mode. it should be noted however that for the transmit message descriptor, tui (bit 11 of tmd0) should be set to 1 for anything trans- mitted in transparent mode. this is done be- cause data transmitted in transparent mode is considered much the same as a ui frame rather than a normal i frame. in transparent mode as in non-transparent mode, the transmit window size (twd) in the transmit descriptor ring pointer must be set to a value greater than 0 for any transmission to occur. in fact, if twd=0 the mk5025 will not poll the transmit descriptor ring. address field filtering and control field operation the frame structure for hdlc is as follows: according to hdlc rules, the a-field may be one or more octets in length. if the lsb of the first oc- tet is 0, then the second octet is also part of the a-field. if the lsb of the second is 0, then the third octet is part of the a-field, and so on until an octet has an lsb = 1. the mk5025 allows the a- field to be one or two octets, depending upon the exta bit (mode register bit 10). the c-field is one octet for modulo 8 for all frames. for modulo 128, the c-field is said to be extended, and is two octets for s (supervisory) and i (information) frames and one octet for u (unnumbered) frames. in the mk5025, address filtering and control field handling applies only to octet aligned frames re- ceived with good fcs. any frame not meeting both of these conditions is discarded and the "bad frames received" error counter (located at iadr + 44 of the initialization block ) is incre- mented. in the transparent mode, address filtering is sup- ported if the prom bit (csr2, bit 10) is 0. in this case, frames are accepted if the received a-field matches either the local station address or the remote station address as specified in the in- itialization block. bit radr in the receive mes- sage descriptor (rmd0 <09>)indicates which of the two programmable adresses the frame matched. this is a one octet compare if the ex- tended address bit, exta is 0 (mode register bit 06), or follows the hdlc rules for extended ad- dressing if exta is 1. frames not matching either address are ignored. extended control is also valid in transparent mode using the extc bit (mode register bit 07), as shown in table 1 and table 2. if extc is 0 then the c-field is one octet for all frames. if how- ever extc is set to 1, the mk5025 will look to see if either of the two least significant bits of the c-field is 0. if so, the frame is said to have an ex- tended control field which is two octets. in addi- tion, bits extaf and extcf (mode register bit 09 & 10) are useful in transparent mode to force extended address and control. if extaf is set along with exta, the receiver will assume the ad- f a c i fcs f where: f = flag a = address field (a-field) c = control field (c-field) fcs = frame check sequence table 1: mk5025 address filtering options exta extaf xide prom dace address filtering 0 x 0 0 1 1 1 0 0 x 0 x 0 0 1 1 0 x 1 x 0 0 0 x 0 1 0 x 0 0 0 x 0 x 0 1 0 1 0 0 single octet filtering l &r (local & remote adresses) no address filtering, all frames accepted single octet filtering l & r and global not allowed double octet filtering l & r per hdlc rules double octet filtering l & r per hdlc rules double octet filtering l & r regardless of a-field lsb not allowed notes: 1) exta = extended address, mode register bit 06. extaf = extended address force, mode register bit 09. 2) xide = xid enabled, csr2 bit 08. prom = promiscuous mode, csr2 bit 10. 3) dace = disable address and control field extraction for load to memory, mode register bit 08. 4) l&r = local and remote addresses. x = do not care. application note 2/4
dress field to be two bytes long regardless of the first bit of the address field. if extcf is set along with extc, the receiver will assume the contol field to be two bytes long regardless of the first two bits of that field. for global adresses, the xide bit is valid in trans- parent mode, depending upon the settings of the other bits in the mode register, as shown in ta- ble 1. if xid is enabled by setting bit xide (csr2 bit 08) to 1, then all frames with address "11111111" are accepted. even frames which are not xid are accepted. in this case, a global address is considered as a command frame. ad- ditionally, frames may transmitted from the xid/test buffer, but neither an address nor con- trol field will be pre-pended to the frame. address and control field extraction can be dis- abled in transparent mode, through use of the if prom bit (csr2, bit 10) and dace bit (mode register bit 08), as shown in table 2. if the prom bit is 1, all frames are accepted. when both the prom bit and the dace bit are set to 1, the device is considered to be in total transparent mode. in this mode no protocol processing is done and all data after the opening flag and be- fore the fcs is loaded into memory. conclusion the mk5025 offers great flexibility to the data communications system designer. the on-chip protocol processing may be used to save the de- signer much time in implementing standard proto- cols such as x.25, lapb, isdn lapd, x.32, and x.75, while still allowing the flexibility of imple- menting alternate or customized hdlc based protocols using the mk5025s transparent mode. table 2: address and control field handling by the mk5025 receiver dace prom exta extaf extc extcf address field handling control field handling 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 1 1 1 x x 0 0 0 1 0 1 0 0 0 1 0 x x 0 1 0 0 1 1 0 1 0 0 1 x x 0 0 0 0 0 1 0 0 0 0 1 x x a filtered a filtered a or ea filtered ea filtered a or ea filtered ea filtered not filtered, aa t mem1 not filtered, aa t mem1 not filtered, aa or ea t mem1 not filtered, ea t mem1 not filtered, aa or ea t mem1 first 2 octest always filtered total transparent mode cc t mem1 cc or ec t mem1 cc t mem1 cc t mem1 cc or ec t mem1 ec t mem1 cc t mem2 cc or ec t mem2 cc t mem2 cc t mem2 ec t mem2 ec t mem1 all data after opening flag & before fcs t memory notes: 1. mem1 is the first location and mem2 is the second location where received data is loaded. mem1 and mem2 are each 16 bits wi de. 2. c is the received, single octet, control field. cc t memx means the single octet control field c is loaded into both bytes of a 16 bit memory location. similarly, a is a single octet address field, and aa t memx means the single octet address f ield a is loaded into both bytes of a 16 bit memory location. 3. ec is an extended control field (2 octets) for received s and i frames. for received u frames, the control field is not ext ended (1 octet). this determines whether cc or ec t memx. however, when extcf is set to 1, the control field is always extended (ec = 2 octets). 4. ea is an extended address field (2 octet s). "a or ea filtered" means that one octet of the a-field is filtered if the lsb = 1, or two octets are filtered if the lsb = 0. similarly "aa or ea t mem1" means that aa is loaded into memory if the lsb = 0; else, ea is loaded. this conforms to hdlc rules for extended address. however, if extaf is set to 1, two octets are filtered re gardless of the lsb, and ea will be loaded into memory. 5. extcf = extended control force, mode register bit 10. 6. dace, prom, exta, extaf, and extc are as defined in the notes for table 1. x = do not care. application note 3/4
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics as sumes no responsibi lity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. spec ifications men- tioned in this publication are subject to ch ange without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical c omponents in life support devi ces or systems wi thout ex- press written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies aust ralia - brazil - france - germany - hong kong - i taly - japan - korea - malay sia - malta - morocco - the netherlands - s ingapore - spain - sweden - switzerland - taiwan - thaliand - united k ingdom - u.s.a. application note 4/4
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